DK-DEV-5SGXEA7N【PDF 15/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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1-6

ALM Resources

SV51002

2014.01.10

ALM Resources

Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive

LUTs (ALUTs) and four registers.

With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations

of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input

LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input

functions.

One ALM contains four programmable registers. Each register has the following ports:

?

?

?

?

Data

Clock

Synchronous and asynchronous clear

Synchronous load

Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control

signals of an ALM register.

GPIO pins or internal logic drives the clock enable signal.

For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives

directly to the outputs of an ALM.

Note: The Quartus II software automatically configures the ALMs for optimized performance.

Figure 1-6: ALM High-Level Block Diagram for Stratix V Devices

shared_arith_in

carry_in

dataf0

Combinational/

Memory ALUT0

labclk

datae0

dataa

datab

6-Input LUT

adder0

reg0

datac

reg1

To General or

Local Routing

datad

datae1

dataf1

adder1

6-Input LUT

Combinational/

Memory ALUT1

reg2

shared_arith_out

carry_out

reg3

ALM Output

The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM

outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also

drive local interconnect resources.

Altera Corporation

Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices

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